The present invention relates to a semiconductor device, and more particularly, to a power metal oxide semiconductor (MOS) transistor.
Recently, there has been an increased rush for power metal oxide semiconductor field effect transistors (MOSFETs) in the markets of switching power supplies for good characteristics of high-current power and high withstand voltage as well as in the market of energy saving switching power supplies for mobile electronic equipment such as a notebook PC. The power MOSFETs dedicated to the mobile electronic equipment are typically used for a power management circuit, an overcharge protection circuit of a lithium cell, and the like.
Among such power MOSFETs, some used in the mobile electronic equipment is strongly desired to have a reduced switching loss as well as enhanced performance of operability at lower supply voltage, which enables a directly operation by a battery. In order to reduce the switching loss, for instance, a resistance upon turning the transistor on (referred to as ON-resistance), a gate-drain capacitance, and a gate resistance must be reduced.
Various indices are used to represent characteristics of the power MOSFET, including a product of the ON-resistance (Ron) multiplied by the electronic charges (Qgd) charged in a gate-drain capacitor, namely, the gate-drain capacitance, Ron×Qgd, and the gate resistance representing a resistance across the gate electrode. Requirements to reduce the switching loss will be lowering both of the indices, Ron×Qgd and the gate resistance.
However, lowering the gate resistance in order to reduce the switching loss leads to an adverse effect of an increase in the product Ron×Qgd. On the other hand, a reduction of Ron×Qgd causes an undesirable increase in the gate resistance. Hence, it's not a simple matter to find a solution of the reduction of the switching loss. This will be detailed below.
FIG. 7 is a cross-sectional perspective view showing a prior art trench-gate power MOSFET. A reference alphanumeric number X designates a device pitch.
On an upper principal surface of an n+ type substrate 21, an n− type epitaxial layer 22 is formed, and then, a p type base layer 23 is further formed on top of the n− type epitaxial layer 22. A trench 24 is dug, extending from an upper surface of the p type base layer 23 down to the underlying n− type epitaxial layer 22. A gate insulation film 25 is deposited to cover side and bottom walls of the trench 24, and then, a gate electrode 26 is deposited inside the gate insulation film 25 to fill the trench 24. On an exposed surface of the gate electrode 26, an interlayer insulation film 28 is disposed. Part of a surface area of the p type base layer 23 alongside the trench 24 is covered with an n+ type source region 29, and the remaining surface area of the p type base layer 23 is coated with the p+ type diffusion region 30. The p+ type diffusion region 30, the n+ type source region 29, and the interlayer insulation film 28 are overlaid with a source electrode (not shown), and on a lower principal surface of the n+ type substrate 21, a drain electrode (not shown) is formed.
In FIG. 7, the above-mentioned ON-resistance Ron is a resistance between the n+ type source region 29 and the n+ type substrate 21. The capacitance Qgd is an electric charge accumulated in a capacitor consisting of the gate electrode 26 and the n− type epitaxial layer 22. A gate resistance is a resistance occurring across the gate electrode 26.
FIG. 8 is a graph schematically illustrating characteristics of drain voltage (ON voltage) and drain current upon turning the power MOSFET in FIG. 7.
In FIG. 8, Vds denotes a drain voltage (voltage between a drain and a source) while Id denotes the drain current.
As can be seen in FIG. 8, at time zero, voltage is applied between the source electrode (not shown) and the gate electrode 26 to turn the gate electrode to positive while voltage is being applied between the drain electrode (not shown) and the source electrode (not shown) to turn the drain electrode to positive. During a delay time before time t1, the drain current Id scarcely flows, but after time t1, the drain current gradually increases till time t2 when the drain current Id reaches a predetermined level. In this state, the device turns on. The above-mentioned ON-resistance Ron is the drain voltage Vds (Vr) at this time divided by the concurrent drain current Id.
As in FIG. 8, a time interval (Tgd) from time t1 to time t2 is identical with a period of time when the gate-drain capacitor is being charged. The switching loss can be expressed by a product of the drain current Id and the drain voltage Vds during the charge period Tgd (an amount of Id from time 0 to time t1 is minimal, and the switching loss during the period is negligible). Thus, the shorter charge period Tgd brings about the accordingly reduced switching loss.
One way of shortening the charge time Tgd is reducing the gate resistance. This is because a reduction of the gate resistance permits electric charge to be rapidly accumulated in the gate-drain capacitor. To attain this, specifically as shown in FIG. 7, the trench 24 may be dimensioned to have a greater depth, thereby increasing a cross sectional area of the gate electrode 26.
This way of reducing the gate resistance results in an increase in an area of the interface between the gate electrode 26 and the n− type epitaxial layer 22 to cause the gate-drain capacitance Qgd to increase, which consequently leads to an increase of Ron×Qgd.